Offset voltages on differential inputs cannot be tolerated for some high-precision applications. One common application is a high-resolution Analog-to-Digital Converter (ADC). An ADC cannot tolerate an input offset that is greater than the least-significant-bit (LSB) since the LSB precision would be lost.
Since the gain-bandwidth product of a single stage amplifier is constant, several amplifier stages are often cascaded together. The cascade provides a desired amplification factor with minimal delay. A cascade of pre-amplifiers can amplify a small input charge to produce a sufficiently large output charge that may then drive a latch that is part of a precision device such as an ADC.
However, any random input offsets in the cascade of pre-amplifiers can be propagated through the cascade of amplifier stages and the final amplified offset can significantly degrade the precision of the system.
Auto-zeroing techniques may be used to cancel such offsets. Often two phases are used to clock the cascade of amplifiers, where offset charges are stored in one phase and signal amplification occurs in the other phase.
Power supply voltages have been reduced to avoid damaging transistors that have been shrunk for advanced semiconductor processes. The lower power-supply voltage results in circuit design challenges since transistor saturation voltages may cut the remaining power-supply voltage in some circuits. The remaining voltage may be further reduced by I*R voltage drops through resistors. Traditional amplifier circuits with a saturated transistor in series with a resistor may leave little room for amplifying transistors to operate when the supply voltage is reduced.
What is desired is a pre-amplifier stage that eliminates an I*R drop due to a resistor in series with a saturated transistor. An amplifier that can operate with reduced power supply voltages is desirable. An amplifier with auto-zeroing and a folded resistor circuit design is desired for precision applications such as for an ADC.
Precision ADC Application—FIGS. 1-2
A pre-amplifier with auto-zeroing of input offsets may be used in a precision ADC application such as described below for FIGS. 1-2. The pre-amplifier may be used for other precision applications such as a low noise amplifier, a high precision instrumentation amplifier, a high precision comparator, any offset cancellation amplifier, DAC, etc.
Successive-approximation ADC's use a series of stages to convert an analog voltage to digital bits. Each stage compares an analog voltage to a reference voltage, producing one digital bit. In sub-ranging ADC's, each stage compares an analog voltage to several voltage levels, so that each stage produces several bits. Succeeding stages generate lower-significant digital bits than do earlier stages in the pipeline.
Algorithmic, re-circulating, or recycling ADC's use a loop to convert an analog voltage. The analog voltage is sampled and compared to produce a most-significant digital bit. Then the digital bit is converted back to analog and subtracted from the analog voltage to produce a residue voltage. The residue voltage is then multiplied by two and looped back to the comparator to generate the next digital bit. Thus the digital bits are generated over multiple cycles in the same comparator stage.
FIG. 1 shows a Successive-Approximation-Register ADC. Successive-Approximation-Register SAR 302 receives a clock CLK and contains a register value that is changed to gradually zero-in on a close approximation of the analog input voltage VIN. For example, the value in SAR 302 may first be 0.5, then 0.25, then 0.32, then 0.28, then 0.30, then 0.31, then 0.315, then 0.313, then 0.312, when comparing to a VIN of 0.312 volts. SAR 302 outputs the current register value to digital-to-analog converter (DAC) 300, which receives a reference voltage VREF and converts the register value to an analog voltage VA.
The input analog voltage VIN is applied to sample-and-hold circuit 304, which samples and holds the value of VIN. For example, a capacitor can be charged by VIN and then the capacitor isolated from VIN to hold the analog voltage. The sampled input voltage from sample-and-hold circuit 304 is applied to the inverting input of comparator 306. The converted analog voltage VA is applied to the non-inverting input of comparator 306.
Comparator 306 compares the converted analog voltage VA to the sampled input voltage and generates a high output when the converted analog voltage VA is above the sampled VIN, and the register value in SAR 302 is too high. The register value in SAR 302 can then be reduced.
When the converted analog voltage VA is below the sampled input voltage, comparator 306 generates a low output to SAR 302. The register value in SAR 302 is too low. The register value in SAR 302 can then be increased for the next cycle.
The register value from SAR 302 is a binary value of N bits, with D(N-1) being the most-significant-bit (MSB) and D0 being the least-significant-bit (LSB). SAR 302 can first set the MSB D(N-1), then compare the converted analog voltage VA to the input voltage VIN, then adjust the MSB and/or set the next MSB D(N-2) based on the comparison. The set and compare cycle repeats until after N cycles the LSB is set. After the last cycle, the end-of-cycle EOC signal is activated to signal completion. A state machine or other controller can be used with or included inside SAR 302 to control sequencing.
Comparator 306 can be replaced with a series of pre-amplifier stages and a final latch. FIG. 2A is a response graph of pre-amplifier and latch stages. The pre-amplifier stages have a negative response shown by curve 312, while the final latch has a positive response as shown by curve 310. For low voltages, curve 312 is above and to the left curve 310, indicating that the pre-amplifiers require less time to achieve the same VOUT voltage than the latch. However, for higher VOUT voltages, curve 310 is above curve 312, indicating that for larger values of VOUT, the latch can achieve these larger voltage outputs much faster than the pre-amplifiers.
FIG. 2B shows a series of pre-amplifiers and a final latch. Pre-amplifier stages 320, 322, 324, 326, 328 are amplifiers that boost the voltage difference between VIN and VA. Especially near the end of comparison when the LSB is being set, the difference between VIN and VA can be quite small. This voltage difference is gradually increased by the pre-amplifier stages until the final stage. Latch stage 330 latches this voltage difference to generate the compare signal that is fed back to SAR 302. Thus stages 320-330 replace comparator 306 of FIG. 1.
By combining a series of pre-amplifier stages with the positive response of the final latch, a fast response time can be achieved. The pre-amplifier stages can gradually amplify and enlarge the voltage difference between VIN and VA until the amplified voltage difference is large enough to drive the final latch. The delay time can be minimized by using low-gain, wide bandwidth pre-amplifiers.
What is desired is a pre-amplifier stage that can be used in a precision ADC. A pre-amplifier that eliminates an I*R drop due to a resistor in series with a saturated transistor and can operate with reduced power supply voltages is desirable. An amplifier with auto-zeroing and a folded resistor circuit design is desired for precision applications such as for the ADC of FIG. 1.